The present invention relates to a semiconductor memory device; more particularly, to a mode register set (MRS) circuit for setting a burst length and a column address strobe (CAS) latency to control operation modes.
FIG. 1 illustrates a schematic circuit diagram of a conventional MRS circuit with a default value of ‘0’. The MRS circuit includes a signal input unit 100 for latching an input signal, a storage unit 110 for saving the default value and an output unit 120 for latching an output of the storage unit 110.
When a MRS enabling signal mrs_en, controlling the signal input unit 100, is in a logic low state, a first PMOS transistor P11 and a first NMOS transistor N11 are turned on. Then, an input signal madd is transmitted to a first node all. The input signal madd is inverted by an inverter I12 and is latched by two inverters I12 and I13. Thereafter, if the MRS enabling signal mrs_en is in a logic high state, a second NMOS transistor N12 and a second PMOS transistor P12 are turned on. The inverted signal at a second node a12 is transmitted to a third node a13. The inverted signal is inverted by an inverter I15 to output as an output signal madd_out1 and latched by inverters I15 and I16. Accordingly, when the MRS enabling signal mrs_en is in a logic low state, the input signal madd is latched. If the MRS enabling signal mrs_en is in a logic high state, the latched input signal is output as the output signal madd_out1.
Considering operation according to the default value stored in the storage unit 110, not according to the input signal, the default value of the MRS circuit described in FIG. 1 will be set at ‘0’. When an initializing signal pwrup1 is activated in a logic high state, a third PMOS transistor P13 is turned on. A signal on the third node a13 is in a logic high state. The output signal madd-out1 is in a logic low state, i.e., with a value of ‘0’, and is output.
FIG. 2 illustrates a schematic circuit diagram of a conventional MRS circuit with a default value of ‘1’. The MRS circuit with a default value of ‘1’ includes a signal input unit 200, a storage unit 210 and an output unit 220, substantially the same as the MRS circuit with a default value of ‘0’ does. The signal input unit 200 and the output unit 220 are identical to those described in FIG. 1. Only the storage unit 210 has a different architecture.
Accordingly, operations according to the input signal are performed in the same manner. The MRS circuits operate differently in respect to the default value. In the MRS circuit with a default value of ‘1’, an NMOS transistor N23 is turned on by the activation of the initializing signal pwrup1. The signal on a node a23 is in a logic low state. The output signal madd-out2 becomes a logic high state. The default value of the MRS circuit described in FIG. 2 will be set at ‘0’.
FIG. 3 illustrates a signal timing diagram of the MSR circuits described in FIGS. 1 and 2. When the initializing signal pwr_up is activated at an initial time ranging from 0 ns to 10 ns, the respective default values are output as the output signals madd_out1 and madd_out2. When the MRS enabling signal mrs_en is activated in a time range of 30 ns to 35 ns, signals at the level of the input signal madd are output as the output signals madd_out1 and madd_out2.
The conventional MRS circuit has a predetermined default value, already set to ‘0’ or ‘1’. Accordingly, it is impossible to change the default value. An artisan should select one of the different kinds of MRS circuits according to the default value required.